Configuring the Micro SRAM instance within a Microsemi SmartFusion2 device involves several key settings to optimize performance and functionality. Here's a breakdown of the configuration options:
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Optimization Mode: You can choose between High Speed and Low Power modes. High Speed prioritizes speed and area efficiency. Low Power mode optimizes for reduced power consumption, potentially using additional logic at the inputs and outputs.
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Port Depth and Width: Each of the three ports (A, B, and C) can be independently configured for depth and width. Port depth ranges from 1 to 32,768, and width ranges from 1 to 1,296. A crucial constraint is that the product of Port A's depth and width must equal the product of Port B's depth and width, and also equal the product of Port C's depth and width.
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Clocking Options: By default, the Micro SRAM uses a single clock (CLK) for all ports. Alternatively, you can enable independent clocks for each port (A_CLK, B_CLK, C_CLK) by disabling the 'Single clock' option.
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Block Select Signals: Ports A and B utilize block select signals (A_BLK, B_BLK) to control read operations. Asserting A_BLK or B_BLK enables reading from the RAM at the specified address.
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Port C Write Enable and Block Select: To write data to Port C, assert C_BLK and set C_WEN high. Data (C_DIN) is then written at the address specified by C_ADDR on the rising edge of C_CLK.
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Pipelining: Ports A and B offer pipelining options for read addresses and read data outputs. Enabling pipelining can enhance performance, but it also introduces latency.
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Register Controls: Address and pipeline registers for Ports A and B include enable inputs, synchronous reset inputs, and asynchronous reset inputs, allowing for customized control based on your design requirements. Consult the Microsemi SmartFusion2 User Guide and the Micro SRAM Instruction Manual for in-depth details and specific parameter settings.
