To configure Error Detection and Correction (EDAC) functionality in your Microsemi SmartFusion2 MSS for blocks like eSRAMs, Cache, Ethernet MAC, USB, and CAN, crucial for radiation-prone environments, follow these steps:
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Configuration Options:
- Expose the EDAC_ERROR Bus: Integrate the EDAC_ERROR bus signal into your FPGA fabric to monitor error events.
- Enable EDAC: Activate EDAC for the following blocks: eSRAM0, eSRAM1, Cache, Ethernet MAC TX and RX RAMs, USB, and CAN.
- Enable EDAC Interrupts: Configure EDAC interrupts for 1-bit errors, 2-bit errors, or both, as needed.
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Port Descriptions:
- Consult the Microsemi SmartFusion2 documentation (Table 2-1) for a comprehensive list of EDAC_BUS signal port descriptions for various blocks, including eSRAM0, eSRAM1, Cache, Ethernet MAC, USB, CAN, and MDDR ECC interrupts.
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Product Support:
- For additional assistance, reach out to the Microsemi SoC Products Group for customer support and technical guidance. Contact details for North America and other regions are available in the product documentation.
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Additional Resources:
- For detailed instructions on configuring the PCIe core and Fabric DDR Controller, please refer to the Microsemi SmartFusion2 User's Guide. Also, utilize the High Speed Serial Interface configurator and DDR Memory Controller configurator within the Libero IP Catalog to streamline your design process.
By carefully following these steps and consulting the Microsemi SmartFusion2 documentation, you can effectively implement EDAC across various critical blocks, enhancing the reliability of your design in radiation-sensitive environments.
