How do I enable Error Detection and Correction (EDAC) for blocks within my Microsemi SmartFusion2 MSS in a radiation-prone environment?

[CooperRose]

To configure Error Detection and Correction (EDAC) functionality for various blocks within your Microsemi SmartFusion2 MSS, especially in radiation-sensitive environments, follow these steps. First, review the configuration options. You can choose to expose the EDAC_ERROR bus to the FPGA fabric. Then, enable EDAC for the following blocks: eSRAM0, eSRAM1, Cache, Ethernet MAC TX and RX RAMs, USB, and CAN. Next, enable EDAC interrupts for the selected blocks. You can configure interrupts for single-bit errors, double-bit errors, or both, depending on your needs. Consult Table 2-1 in the Microsemi manual for detailed port descriptions of the EDAC_BUS signals associated with each block, including eSRAM0, eSRAM1, Cache, Ethernet MAC TX and RX RAMs, USB, CAN, and MDDR ECC interrupts. For more detailed information on configuring the PCIe core and Fabric DDR Controller, please refer to the Microsemi SmartFusion2 User's Guide and utilize the High Speed Serial Interface configurator and DDR Memory Controller configurator within the Libero IP Catalog. If you need additional help, contact Microsemi SoC Products Group for customer service and technical support. Contact details are available in the manual for North America and the rest of the world.