Summary: Seeking an experienced FPGA Design Engineer with strong VHDL skills and deep experience in bring-up, external digital interfaces, and packet handling. Highlights: 1. Opportunity for an experienced FPGA Design Engineer 2. Requires strong VHDL skills and deep bring-up experience 3. Focus on packet handling and external digital interfaces Title: FPGA Design Engineer Location: San Diego (Onsite) Term: Contract Duration: Long Term Start: ASAP Required: Active Clearance Requirements 10+ years experience FPGA Design Engineer, .Strong VHDL Skills, Deep experience with Bring-Up, Experience in Cryptography is preferred. Good experience with Packet handling and External digital interfaces Required. Experience with Microchip FPGAs a Plus Active Government Clearance Required Onsite Full-Time Required Benefits A2e Does NOT Accept Unsolicited Resumes or Referrals from any source other than the candidate, and, as a result, we will not be considering any unsolicited referrals or resumes sent to us as a fee -based candidate submittal. Any unsolicited resumes sent to A2e, including unsolicited resumes sent to a A2e mailing address, fax machine or email address, directly to A2e employees, or to A2e’s resume database will be considered A2e property. A2e will NOT pay a fee for any placement resulting from the receipt of an unsolicited resume. Agencies are hereby specifically directed NOT to contact A2e employees, A2e’s recruiting team, or other authorized A2e personnel, in an attempt to present candidates.
Workable · HR
Workable · HR
