Design For Test Engineer IV (IC)
$112,200-170,500/year
Full-time
Onsite
CaliforniaSummary: Seeking a Design For Test Engineer IV with expertise in DFT implementation for networking chips, scan-insertion, ATPG, MBIST, and silicon deb
- Execute DFT implementation for 3nm and 5nm Networking chips and IP.
- Perform scan-insertion, ATPG pattern generation, and pattern simulation.
- Involve in MBIST insertion and verification, and silicon debug.
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