Design For Test Engineer III (IC)

Summary: This role involves DFT implementation for networking chips, RTL checks, scan-insertion, ATPG pattern generation, pattern simulation, and sili
- Engage in cutting-edge 3nm and 5nm Networking chip DFT implementation.
- Work with industry-leading tools like Tessent, Modus, Tetramax, and VCS.
- Contribute to DFT flow enhancement and automation through scripting.






