Design For Test Engineer IV (IC)

Summary: Seeking a Design For Test Engineer IV to implement DFT for advanced networking chips, perform RTL checks, scan-insertion, ATPG, and pattern s
- Engage in DFT implementation for 3nm and 5nm Networking chips and IP DFT work
- Utilize scripting with Perl, Shell, and TCL for flow enhancement
- Contribute to silicon debug and bring-up for block and top designs






