Elevate Semiconductor
Senior Digital Design Engineer
San Diego, CA, USA
At Elevate Semiconductor, our mission is to empower semiconductor and system test customers by delivering world-class test integrated circuits (ICs) that tackle the industry's most complex automated test equipment (ATE) challenges. We pride ourselves on exceeding expectations by designing the lowest power, highest density solutions to achieve the lowest possible cost of testâboth today and for the future.
We are seeking a talented Senior Digital Design Engineer to play a critical role in the design and verification of digital circuits for ATE ASICs. In this position, you will collaborate closely with project leads to define functional requirements and work alongside our analog design team to seamlessly integrate digital circuits into devices.
Responsibilities include defining timing constraints, performing synthesis, floor planning, place and route (PnR), and timing analysis to achieve a finalized digital layout. Additionally, youâll contribute to system verification by developing SystemVerilog or UVM testbenches and tests to validate device functionality. You may also support physical implementation to ensure an accurate and robust final design.
Please note:Â At this time, we are unable to offer visa sponsorship for this position. Candidates must be authorized to work in the United States without current or future sponsorship requirements.
Responsibilities
As the sole Digital Design Engineer in the organization, you will own the entire digital design flow from concept to implementation. Your responsibilities will include:
Analyze design requirements and contribute to defining the final digital circuit.
Develop digital circuits using SystemVerilog.
Create testbenches and tests to verify digital circuit functionality.
Collaborate with the ASIC team to integrate digital functions into the device.
Define timing constraints and ensure they are met throughout the design process.
Partner with the physical implementation team to achieve timing and area goals.
Utilize synthesis, place-and-route (PnR), and static timing analysis (STA) tools to optimize performance and layout.
Requirements
Bachelorâs degree in Electrical Engineering (required).
Minimum of 6 years of experience in digital semiconductor circuit design.
Proficiency with Cadence tool flow.
Knowledge of verification methodologies.
Expertise in SystemVerilog.
Familiarity with synthesis, place-and-route (PnR), and static timing analysis (STA) tools.
Excellent verbal and written communication skills.
Preferences:
Familiarity with UVM is a plus.
Experience with scripting languages is advantageous.
Hands-on experience with benchtop or ATE testing is preferred.
Why Join Us?
At Elevate Semiconductor, youâll be part of a dynamic team working on innovative technologies that shape the future of the semiconductor industry. We offer competitive compensation, comprehensive benefits, and opportunities for professional growth in a collaborative environment.
Apply Today!
If you are passionate about digital design and eager to contribute to groundbreaking semiconductor solutions, we want to hear from you!
Benefits
100% Employer Paid Health Insurance (Medical, Dental, Vision)
Unlimited Paid Time Off
Performance Bonuses
Free Lunch Catered in by Local Restaurants
Private Equity Options
Retirement Plans
Sabbatical Program
Tuition Reimbursement
Volunteer Days
Relocation Assistance
Conference Attendance Support
Biweekly Phone Stipend
Employee Assistance Program
The salary range for this role is $140,000-$160,000.00.
While a salary range is provided, the final compensation will depend on your experience, skill set, and how well you're able to highlight your background throughout the interview process.
$140,000-160,000
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